1. Field of the Invention
The present invention relates to a pulse signal generating circuit and a semiconductor memory device, and in particular, relates to a pulse signal generating circuit for controlling a refresh operation.
1. Description of the Background Art
FIG. 9 is a block diagram showing a general structure of a dynamic random access memory (will be referred to as "DRAM"). The DRAM is formed on a semiconductor chip CH.
A memory cell array 1 includes a plurality of word lines, a plurality of bit lines crossing the plurality of word lines and a plurality of memory cells arranged at crossings thereof. Each memory cell includes a capacitor for storing data and an N-channel transistor. The N-channel transistor is connected between the capacitor and the bit line, and has a gate connected to the word line.
An RAS buffer 2 receives an external row address strobe signal/RAS, and generates an internal row address strobe signal/RASI. A CAS buffer 3 receives an external column address strobe signal CAS, and generates an internal column address strobe signal/CASI. A WE buffer 4 receives an external write enable signal/W, and generates an internal write enable signal/WI.
In a normal operation, a row address buffer 5 receives an external address signal ADD through a switch 17, and generates a row address signal in response to the internal row address strobe signal/RASI. A row decoder 6 is responsive to the row address signal to select one of the plurality of word lines in the memory cell array 1. A word driver 7 drives the word line selected by the row decoder 6 to a predetermined voltage. Thereby, data is read from the plurality of memory cells connected to the selected word line onto the corresponding bit line pairs. The data read onto each bit line pair is amplified by a sense amplifier 8.
A column address buffer 9 receives an external address signal ADD, and generates a column address signal in response to the internal column address strobe signal/CASI. A column decoder 10 is responsive to the column address signal to select one of the plurality of bit line pairs. Thereby, the selected bit line pair is connected to an input/output line pair.
In a write operation, externally applied input data D is sent to the input/output line pair through an I/O circuit 11. In a read operation, data on the input/output line pair is supplied outside the chip as output data D through the I/O circuit 11.
A control circuit 12 is responsive to the internal row address strobe signal/RASI, internal column address strobe signal/CASI and internal write enable signal/WI to generate various control signals for controlling various parts.
A self-refresh changing circuit 13, an internal address generating circuit 14, a pulse signal generating circuit 15 and a timer 16 form a refresh control circuit.
When a refresh enable signal REFE supplied from the timer 16 attains an active state (e.g., high level), a refresh operation is carried out. In the refresh operation, the row decoder 6 is responsive to the row address signal to select one of the plurality of word lines in the memory cell array 1. The word driver 7 drives the word line selected by the row decoder 6 to a predetermined voltage. Thereby, data is read from the plurality of memory cells connected to the selected word line onto the corresponding bit line pairs. The data read onto each bit line pair is amplified by the sense amplifier 8.
Thereafter, the voltage of the word line is restored to the ground voltage. Thereby, the data on the plurality of bit line pairs amplified by the sense amplifier 8 is written into the plurality of memory cells connected to the selected word line, respectively. In this manner, the data in the plurality of memory cells connected to the selected word line is refreshed.
Now, a self-refresh operation of the DRAM in FIG. 9 will be described below with reference to a timing chart of FIG. 10.
The self-refresh changing circuit 13 receives a clock signal .phi..sub.E from the control circuit 12. The self-refresh changing circuit 13 applies a self-refresh control signal SREF to the internal address generating circuit 14, the pulse signal generating circuit 15, the timer 16 and the switch 17.
In FIG. 10, when the external row address strobe signal/RAS falls to the low level at time t1 after the external column address strobe signal/CAS fell to the low level (i.e., in a CAS before RAS cycle), the refresh enable signal REFE supplied from the timer 16 rises to the high level. Thereby, the above refresh operation is carried out.
The self-refresh changing circuit 13 counts pulses in the clock signal .phi..sub.E, and changes the self-refresh control signal SREF into the active state (i.e., high level) at time t2 after the elapsing of a predetermined time period from the time t1. This activates the internal address generating circuit 14 and pulse signal generating circuit 15, so that the self-refresh operation starts.
The internal address generating circuit 14 sequentially generates the refresh address signals indicative of the refresh address. The pulse signal generating circuit 15 generates a pulse signal .phi. of a constant period. The timer 16 counts pulses in the pulse signal .phi..
When the timer 16 counts a predetermined number of pulses, it raises the refresh enable signal REFE to the high level, and thereafter, lowers the refresh enable signal REFE to the low level when it counts a predetermined number of pulses. In this manner, the timer 16 is responsive to the pulse signal .phi. to repetitively and alternately change the refresh enable signal REFE to the high and low levels at a constant period T3.
The RAS buffer 2 is responsive to the refresh enable signal REFE to alternately change the internal row address strobe signal/RASI to the high and low levels.
The row address buffer 5 is responsive to the fall of the internal row address strobe signals/RASI to sequentially apply the refresh address signals, which are received from the internal address generating circuit 14, to the row decoder 6. The row decoder 6 is responsive to the refresh address signals to sequentially select the word lines in the memory cell array 1. Thereby, the data in the memory cells connected to the selected word line are refreshed.
The above operation is repeated until the external row address strobe signal/RAS rises to the high level.
In FIG. 10, the refresh operation is carried out during a period T1 from the time t1 to the time t2, and the self-refresh operation is carried out during the period T2 from the time t2 to the time t3.
As described above, the refresh period T3 in the self-refresh operation depends on the counting number of pulses of the pulse signal .phi. by the timer 16.
FIG. 11 shows a structure of the pulse signal generating circuit 15. The pulse signal generating circuit 15 includes a plurality of inverters G1 which are mutually connected in a ring form. The plurality of inverters G1 form a ring oscillator. The pulse signal .phi. is sent from a node n1 between two of the inverters G1 of this ring oscillator.
FIG. 12 is a circuit diagram showing the inverter. The inverter G1 includes a P-channel MOS transistor P1 and an N-channel MOS transistor N1. The transistor P1 is connected between a node n2 and a node n5, and has a gate connected to a node n4. The transistor N1 is connected between the node n5 and a node n3, and has a gate connected to the node n4. The node n2 is connected to a power supply terminal which receives a supply voltage Vcc. The node n3 is connected to a ground terminal which receives a ground voltage (0 V).
If the inverter G1 is to be activated and inactivated in response to the self-refresh control signal SREF, a transistor is connected between the power supply terminal and the node n2 or between the ground terminal and the node n3. This transistor has a gate receiving the self-refresh control signal SREF.
As described above, in the DRAM, the refresh period T3 in the self-refresh operation depends on the counting number of pulses of the pulse signal .phi. generated from the pulse signal generating circuit 15. If the operation temperature of the DRAM is high, a data holding time of a memory cell is short. Therefore, the refresh period T3 must be short at a high temperature.
In the conventional DRAM, the counting number of pulses of the pulse signals .phi. by the timer 16 is set at a relatively small value in view of the worst condition at a high temperature. Thus, the refresh operation is carried out at a short period regardless of the high and normal temperatures.
Consequently, the refresh operation is carried out at a short period, which has an excessively large margin with respect to leak of data, at the normal temperature. This results in extra power consumption at the normal temperature.